1. Field of the Invention
The present invention relates to a signal processing circuit used in a digital serial interface and a method of the same.
2. Description of the Related Art
In recent years, as an interface for transfer of multimedia data, the IEEE (Institute of Electrical and Electronic Engineers) 1394, High Performance Serial Bus for realizing high speed data transfer and real time transfer has become the standard.
The types of data transfer of this IEEE 1394 serial interface include asynchronous transfer for requests, requests for acknowledgement, and confirmation of reception of the related art and isochronous transfer with which the data is sent at one time from a certain node at 125 xcexcs.
In this way, with an IEEE 1394 serial interface having such two transfer modes, data is transferred in units of packets.
FIGS. 4A and 4B are views of the byte size of a source packet in isochronous communication. FIG. 4A shows the size of a packet in the digital video broadcast (DVB) method; while FIG. 4B shows the size of a packet in the digital satellite system (DSS) method.
The source packet in the DVB method is comprised of 192 bytes, that is, 4 bytes of a source packet header (SPH) and 188 bytes of inherent transport stream data, as shown in FIG. 4A.
Contrary to this, the source packet in the DSS method is comprised of 144 bytes, that is, 4 bytes of a source packet header (SPH), 10 bytes of additional data (AD0 to AD9), and 130 bytes of inherent transport stream data, as shown in FIG. 4B.
The additional data is inserted between the source packet header and the data. Note that, in the IEEE 1394 standard, the unit of minimum data able to be handled is one quadlet (=4 bytes=32 bits), therefore the transport stream data and the additional data must be set to be able to be comprised in total of 32 bit units.
Note that at the default, no additional byte is set.
FIG. 5 is a view of an example of a correspondence between the original data when data is transmitted in the isochronous communication of the IEEE 1394 standard and the packets actually transmitted.
As shown in FIG. 5, each of the source packets of the original data is given a source packet header of 4 bytes and padding data for adjusting the data length and then is divided into a predetermined number of data blocks.
Note that since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks, various headers, etc. are all set to multiples of 4.
FIG. 6 is a view of the format of the source packet header.
As shown in FIG. 6, in 25 bits in the source packet header is written a time stamp utilized for suppressing jitter when for example MPEG (Moving Picture Experts Group)-TS (Transport Stream) data utilized in a digital satellite broadcast etc. of the above DVB method is transmitted by isochronous communication.
Such a packet header, a common isochronous packet (CIP) header, or other data is then added to a predetermined number of data blocks so as to produce the final packets.
FIG. 7 is a view of an example of the basic configuration of an isochronous communication use packet.
As shown in FIG. 7, in a packet for isochronous communication, the first quadlet is comprised of a 1394 header, the second quadlet a Header-CRC, the third quadlet a CIP-header 1, the fourth quadlet a CIP-header 2, the fifth quadlet a source packet header (SPH), and the sixth quadlet and subsequent quadlets the data regions. The final quadlet is a Data-CRC.
The 1394 header is comprised by a xe2x80x9cdata-lengthxe2x80x9d representing the data length, a xe2x80x9cchannelxe2x80x9d indicating number of the channel (one of 0 to 63) transferred through this packet, a xe2x80x9ccodexe2x80x9d representing a code of processing, and a synchronous code xe2x80x9csyxe2x80x9d prescribed by each application.
The Header-CRC is an error detection code of the packet header.
The CIP-header 1 is comprised by an source node ID (SID) region for the transmission node number, a data block size (DBS) region for the length of the data block, a fraction number (FN) region for the number of divisions of the data in the formation of the packet, a quadlet padding count (QPC) region for the number of the quadlets of the padding data, a source packet header (SPH) region for the flag showing the existence of the source packet header, and a data block continuity counter (DBC) region for the counter for detecting the number of isochronous packets.
Note that the DBS region shows the number of the quadlets transferred through one isochronous packet.
The CIP-header 2 is comprised by an FMT region for the signal format showing the type of the data to be transferred and a format dependent field (FDF) region utilized corresponding to the signal format.
The SPH header has a time stamp region in which is set a value obtained by adding a fixed delay value when the transport stream packet.
Further, the data CRC is the error detection code of the data field.
The signal processing circuit of the IEEE 1394 serial interface for the transmission and reception of packets having the above structure is mainly constituted by a physical layer circuit for directly driving the IEEE 1394 serial bus and a link layer circuit for controlling the data transfer of the physical layer circuit.
In the isochronous communication system in the IEEE 1394 serial interface, as shown in for example FIG. 8, the link layer circuit 2 is connected to an application, that is, MPEG transporter 1, while the link layer circuit 2 is connected to a serial interface bus BS via a physical layer circuit 3.
In the transfer of data of the IEEE 1394 serial interface, the transmission data and reception data are stored once in a storage device such as a first-in first-out (FIFO) memory (hereinafter simply referred to as an FIFO) provided in the link layer circuit 2. In actuality, an asynchronous packet use FIFO and an isochronous packet use FIFO are separately provided.
Sometimes, however, as mentioned above, one source packet of the usual MPEG transport stream is transmitted divided.
In this case, at the reception side, it is necessary to judge the first packet of the source packet from the packets sent divided and store the same in the FIFO.
Further, since they are sent divided, if a packet being transmitted is lost due to noise or other factors, normal storage of data is no longer possible.
In the current IEEE 1394 serial interface signal processing circuits, however, no system has been established for processing received packets transmitted divided.
The present invention was made in consideration with such a circumstance and has as an object thereof to provide a signal processing circuit capable of determining and storing a starting packet at the time of reception of divided packets by a serial interface and capable of realizing normal storage of data when packet loss occurs and a method of the same.
To achieve the above object, the present invention provides a signal processing circuit for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and outputting the packet data to an application side, having a means for selecting a desired packet from among the received divided packets.
Further, the present invention provides a signal processing circuit for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and given control information indicating the number of transmission packets and outputting the packet data to the application side, having a means for deciding whether or not a packet is a starting packet from predetermined bit information of the control information given to the received divided packets.
Further, the present invention provides a signal processing circuit for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and given first control information indicating the number of transmission packets and second control information indicating the number of divided packets and outputting the packet data to the application side, having a reception circuit for taking an AND logic of the first control information given to the received divided packets (value obtained by subtracting 1 from the power of 2 defining the value of the second control information as the power) and deciding the reception packet of 0 as the result of this decision as the starting packet.
Further, the present invention provides a signal processing circuit for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and given control information indicating the number of transmission packets and outputting the packet data to the application side, having a predicting means for predicting the value of the control information of the packet received next from the control information given to a received divided packet and a determining means for comparing the control information value of the currently received packet and the prediction value predicted by the predicting means and determining an occurrence of packet loss where they do not coincide.
Further, the present invention provides a signal processing method for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and given control information indicating the number of transmission packets and outputting the packet data to the application side, comprising the steps of predicting the value of the control information of the packet received next from the control information given to a received divided packet and comparing the control information value of the currently received packet and the predicted prediction value and determining packet loss when they do not coincide.
Further, the present invention provides a signal processing method for receiving packet data transmitted in a divided manner through a serial interface bus in a predetermined time cycle and given control information indicating the number of transmission packets, storing this once in the storing means, and outputting the packet data to the application side, comprising the steps of predicting the value of the control information of the packet received next from the control information given to a received divided packet; comparing the control information value of the currently received packet and the predicted prediction value and determining packet loss where they do not coincide; storing all of the currently received data if the pointer position before storage is the start of the bank of the storing means when the current reception data is received where it is determined that packet loss occurs; and storing the next source packet from the next address at which the source packet which was normally stored the previous time is stored where the pointer position before storage is not the start of the bank.
According to the signal processing circuit of the present invention, for example, the signal reception circuit judges if a packet is the starting packet from the predetermined bit information of the control information given to the received divided packet.
For example, the AND logic of the first control information given to the received divided packet and the (value of 2 to the power of the value of the second information minus 1) is taken and the received packet with a result of 0 is judged as the starting packet.
Further, according to the signal processing circuit of the present invention, a predicting means predicts the value of the control information of the packet to be received next from the control information given to the received divided packet. Further, the deciding means compares the value of the control information of the currently received packet and the prediction value predicted by the predicting means and decides that packet loss has occurred when they do not coincide.
Further, according to the signal processing method of the present invention, the value of the control information of the packet to be received next is predicted from the control information given to a received divided packet and the control information of the currently received packet and the predicted value are compared. When the result of the comparison is noncoincidence, it is decided that a packet was lost. When it is decided that a packet loss has occurred, all of the currently received data is stored when the pointer position before storage when the current reception data was received was the start of the bank of the storing means while the next source packet from the next address at which the previous normally stored source packet was stored is stored when the pointer position before storage was not the start of the bank.